The developing density of incorporation and the expanding level of a system-on-chip memory possessed by embedded programs have prompted an expansion in the normal amount of the power consumption. Thus, the wast-case execution time has implemented in order to reduce the integrity and iterations of the programs. The clock cycles which is required in every instruction of the program can be reduced by observing the WCET and it is similarly expanding the memory utilization depends on both ROM and RAM in the embedded systems and power utilization criteria 12. Thus, for achieving the worst-case execution time minimization for the real-time embedded system, a compiler named WCET-aware rescheduling register allocation has used to do that. The impacts of register allocation, instruction planning, and cluster assingment on the nature of the created code which are considered for worst-case execution time minimization are the novelty of the suggested approach 12. In this research, three compilation processes are coordinated into a solitary phase balanced result acquired with 6 kbytes of ROM reduction from 8 kbytes.