College Papers

For the proposed RHBD 10T memory cell

For the proposed RHBD 10T memory cell, Fig. 1 describes its
basic schematic structure. From this figure, it can be seen that
the proposed RHBD memory cell consists of ten transistors in
which PMOS transistors are transistors P1 P6, and the remaining
transistors (N1 N4) are NMOS transistors. Both NMOS transistors
N4 and N3 are defined as the access transistors, and their gates are
connected with a wordline (WL). Hence, when this WL is in high
mode (WL = 1), two access transistors are turned ON. At the moment,
write/read operation can be implemented. The stored nodes are nodes
Q, QN, S1, and S0 in which these four nodes are responsible for
keeping the stored value correctly. In order to quickly transmit the
digital signal to the output port during a read operation, a differential
sense amplifier has to be employed and connected with two bit lines
BL and BLN.