College Papers

Final Project Report CRC Encoder and Decoder – VHDL Beshoy Hanna I

Final Project Report
CRC Encoder and Decoder – VHDL

Beshoy Hanna
I.D # – 1001250363
Electrical Engineering
University of Texas at Arlington
Arlington, Texas
[email protected]

Abstract— For the final project of Digital Design and Microcontrollers, students explored and designed a VHDL code in order to familiarize themselves with a common error detection algorithm known as the Cyclic Redundancy Check (CRC), serving as an error detection check for transmitting digital signals. With an outgoing signal having an attached code to them, the CRC works by checking the incoming signal upon receiving to ensure both signals match. Once the CRC check verifies that the codes indeed match, the data is current and valid, however, if the codes do not match, then corruption of data is present and must be addressed. Within this final project, an 8-bit CRC must be made by using an example 4-bit CRC based code.
A CRC, or cyclic redundancy check, is a code that uses a checksum based process algorithm to detect inconsistency or errors in a given data stream, specifically individual corrupt bits of data. With the checksum algorithm process, the CRC acts as a checker, attached to the end of the data stream, enabling the receiver of the data to detect such errors as previously stated when transmitted. Typically, these are errors in data being transmitted, which consist of such signals including informational data of telecommunication networks and even storage devices such as hard disk drives located within every computer. This fundamental shows why a CRC check is sometimes vital for the smooth and error free operation of certain electrical components and data transmission. In order to complete this project, the use of VHDL language in code was required to be utilized. VHDL is a language that is important to many electrical engineers in various fields of work as it is constantly used as a language in coding of hardware devices as well. Simulating certain hardware allows for testing of possible designs along with certain program algorithms such as the CRC.
In this project, students were instructed to use a 4-bit CRC checksum code and edit it in order to use an 8-bit CRC checksum.

The given generator polynomial by the project procedures 1 in order to accomplish this project can be seen below in Figure 1.

Figure 1. (Feedback Shift Register Implementation of CRC Checksum Generator)

In order to get started with this project, several class lectures introduced and explained the structure of how the code language of VHDL works. VHDL consists of five basic building blocks, which include respectively, the Package, Entity, Configuration, Architecture, and lastly the Library to be used with a code. Starting with the package, commonly used functions and constant components are expressed. Moving onto the entity, a brief interface description is then realized about the program. Furthermore, the architecture then details the descriptive functionally of the program. Lastly, the essential configuration block helped connect the entity into the architecture portion of the code. Using this background knowledge of the language of VHDL, students were given a sample CRC code using 4-bits through blackboard 1 to explore and go over the design of the code and how it works. Using the given sample code, students could then begin to edit the given code and use it as a template in building the 8-bit CRC checksum code. To get started, students were instructed to download and activate a student version of the Active-HDL software, which would be used to compile and run the CRC code.

In order to create the 8-bit based project, a new project was firstly created in VHDL and the sample code files were added to the library. The files were compiled and checked for errors as a basis for starting, which no errors came about as expected. Then, the simulation was run to see if the code transmitted the data correctly and the output of the complied files could also be directly found thereafter. These output files could be found under the ‘my designs’ folder of the main hard drive of the computer. Once there, the designated design name of the project could then be opened in order to furthermore view the output files of the complier, named CRCOUT1.txt and CRCOUT2.txt.
Once the process of the given sample encoder and decoder was understood, proper modifications could then be made in order to allow for an 8-bit CRC code to correctly be complied. The new 8-bit CRC code would need to accept a larger code and use a new polynomial to create the checksum based value. In order to accomplish this, some important and critical changes were required to be implemented to the code to ensure proper success and use of the 8-bit based CRC. Firstly, the input vectors for both the encoder and decoder needed to be changed from 4 -bits (3 to 0) to 8-bits (7 to 0), respectively. Alongside this change, the temporary vector was also adjusted from “0000” to “00000000”, in order to account for the extra bits added. Furthermore, the XOR process had to be lengthened to account for the increase of the number of bits encoded and decoded on both portions of the code. Additionally, the “behavioural” process was changed to “crc8_16b_arch” and accounted for 23 bits instead of 19 bits, as given from the sample code. After completion of these main changes, a few lines of supplemental description were added alongside the code by using ‘- -‘ to comment the words out of the code from compiling. Once the code had all the proper adjustments made, a given test bench file for an 8-bit CRC was also added into the project 1 on Active-HDL in order to compile the code correctly into using certain vectors and checking for their respective outputs as a means of accuracy for the code. Running the code with the test bench for 8-bits was used to see if the new 8-bit CRC code was correctly producing the CRCOUT text files with the proper output. With successful completion of the complied files, Active-HDL showed 0 errors ensuring a successfully complied file. In order to visualize the structure of how the code behaved, a new waveform was selected from the top row of operations from within the program, and the entire program was set to ‘Run-For’ 1000 nanoseconds. Selecting ‘initialize simulation’ then allowed for the user to grab and drop the entire complied architecture into the new waveform and visualize the behavior of how the code was operating.

Figure 2 below shows the output of the waveform produced from Active-HDL after initializing the complied code for the 8-bit CRC.

Figure 2. (A cropped sample of the produced waveform of the 8-bit CRC as seen through Active-HDL)

The waveform shows that the changes happened at the rising edge instead of the falling edge. It also shows that transmission was successful.
It can be concluded that the CRC does not fix data in the code, it only detects errors. Also, the polynomial that is used must be a multiple of X+1, because using any polynomial can provide an incorrect remainder.
1 Roth Fundamentals of Logic Design 7th c2014